Hyper Analytix is developing a next-generation verification solution that fundamentally alters the resource and schedule model that underlies a typical verification project. Our approach is to apply state-of-the-art technology in the context of commonly accepted verification methodologies in a way that is easily deployable and scalable from the smallest blocks all the way to full-chip. Our mission is to reduce the cost of functional verification by a factor of between 2 and 5X.
Today, the efforts of established EDA vendors tend to focus on a few areas:
- Incremental improvements to existing verification technology, such as pre-packaged "methodologies" like VMM and OVM.
- Improved simulation run time through improved simulation algorithms, parallel computing hardware, or hardware acceleration.
- Niche solutions, such as formal verification.
While these areas are certainly important, they do not radically alter the overall cost and schedule for a typical verification project. Incremental improvements are just that − incremental. Improved run times are helpful, but they often exacerbate the human resource cost. And niche solutions have limited scope and uncertain return-on-investment.
What's really required is a new approach that allows verification and design engineers to work at much higher levels of abstraction while letting the tools do the grunt work. This will radically reducing the amount of effort and schedule required to achieve verification closure.
Our story is still unfolding and we will expand the information on this website as it makes sense. Until then, you may be interested in the following additional information:
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