Verification pain

Resource pain

Moore’s law has continued unabated for many years and is poised to continue for many more years. The exponential increase in the capability of silicon to support higher and higher complexity has led IC and system houses to create ever larger and more complex devices. As devices have grown, so too has the cost of functional verification of these devices. This has led to a situation where companies devote upwards of 70% of their budget to verification.

Schedule pain

Even with this level of investment, verification is often the limiting factor in getting chips to paying customers. There are two major limiters to the cost and schedule for a verification project.

First, test bench development can take as much or more effort as the original logic design. The level of detail the a verification engineer must deal with may be less, but the uncertainty as to where bugs may lie causes the verification engineer to expend a large effort creating scenarios that might (but often will not) uncover bugs.

Second, to gain the necessary confidence that the design is functionally correct, the verification process must achieve coverage closure. That is, the sum total of all the verification tests must sufficiently test all of the specified functions of the design. Unfortunately, due to the complexity of design in conjunction with the random nature of most test benches, it can take many months to achieve a sufficient level of test coverage to achieve high confidence that the design is "good enough"

Predictability pain

Compounding the resource and schedule pain is the fact that even with large schedule and resource investments, functional bugs still often go undetected until prototypes are back from the fab. The sad fact is that functional bugs are the single largest source of bugs in failing first silicon. The figure to the right contains statistics published by Collett International Research that show that 60% of designs that fail first silicon have functional bugs. In comparison, the next most important category of bugs is present in 33% of designs that fail first silicon, a rate that is about half that of functional bugs. Since it costs millions of dollars to create photo masks in preparation to fabricate a chip and since it can take upwards of three months to receive a prototype part, these undetected functional bugs are very expensive.

The fundamental problem here is with predictability of the verification process. Design managers do not choose to prototype buggy designs. Rather, they predict, based on a variety of quantitative and qualitative measures, whether there are any important bugs remaining. They do not stop the verification process until they predict that there are no unfound bugs. But if the verification process does not provide good predictability, then the design manager may inadvertently release a buggy design.