Posted on 04/14/2010 - 23:41
by JL Gray
from the site Cool Verification
This post is for all of those lonely EDA vendors out there, wondering whether or how they're going to attract customers at the upcoming Design Automation Conference. You may have heard of Xuropa. Xuropa started out a couple of years......
Posted on 04/11/2010 - 22:20
by JL Gray
from the site Cool Verification
Some of you may have seen an announcement on Friday describing an early adopter kit of the UVM "based on the Accellera Verification IP Technical Subcommittee (VIP-TSC) decisions to date". Being a member of the Accellera VIP-TSC myself, I can......
Posted on 03/10/2010 - 09:09
by JL Gray
from the site Cool Verification
Hi everyone. Last night I wrote a post describing the debate over whether or not to include a register package in the UVM. The link to the survey was broken if you read the post in your email client or......
Posted on 03/09/2010 - 22:32
by JL Gray
from the site Cool Verification
Many of the Accellera VIP TSC members are in Marlborough, MA this week discussing what features should be part of the first release of the new UVM (Unified Verification Methodology). For those of you who are not familiar, the UVM......
Posted on 02/17/2010 - 09:00
by JL Gray
from the site Cool Verification
For those of you who have not been paying attention, DVCon 2010 starts next week. In a previous post I described several events I'll be involved with except for one very important item. This year I will be moderating the......
Posted on 02/16/2010 - 23:24
by JL Gray
from the site Cool Verification
In the beginning, there was SystemVerilog, and it was good. Through it some testbenches were made; without it other testbenches were made. In SystemVerilog was light, but also darkness in the form of a set of missing features that had......
Posted on 01/25/2010 - 00:37
by JL Gray
from the site Cool Verification
Now that the SystemVerilog 2009 standard has been released, the P1800 working group is getting ready to start work on the next version of the SystemVerilog standard. As part of that effort, they are soliciting feedback in preparation for an......
Posted on 01/22/2010 - 13:23
by JL Gray
from the site Cool Verification
As a potential user of the UVM, would you like to be able to view active development branches within the live UVM repository, or should this information be hidden until official releases are made?...
Posted on 01/22/2010 - 13:13
by JL Gray
from the site Cool Verification
Yet another Accellera call about the Unified Verification Methodology (UVM) is underway. My takeaway? Both EDA and user companies put such a premium on secrecy that a truly open development process is simply not possible. Based on its current trajectory,......
Posted on 10/20/2009 - 22:13
by JL Gray
from the site Cool Verification
In a fascinating (to me) twist of fate, I will be moderating a panel on the “next big thing” in formal methods at FMCAD 2009 in Austin, Texas. The panel, entitled “What will be the next breakthrough solutions in formal?”......
