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CoreConnect Bus and AMBA Bus Specification Resources

Posted on 04/16/2009 - 01:01 by from the site ASIC-System On Chip (SoC)-VLSI Design

"CoreConnect" and "AMBA" are the two prominent bus architectures used in System on Chip designs. These architectures define technology independent standard bus protocol methodologies for easy integration of IPs within a System on Chip design. "CoreCOnnect" is mainly developed by IBM and integral part of PowerPC processor based System on Chip designs.CoreConnect bus architecture has three parts:1. PLB: Processor Local Bus2. OPB: On chip Peripheral Bus3. DCR: Device Control Register BusThese specifications can be downloaded from IBM website."AMBA" stands for "Advanced Microcontroller (Microprocessor) Bus Architecture". AMBA specifiation is developed by ARM and extensively used in ARM based System on Chip designs.AMBA has different versions as listed below from the lowest version:1. ASP: AMBA Advanced System Bus2. APB: AMBA Advanced Peripheral Bus 3. AHB: AMBA Advanced High performance Bus4. AXI: AMBA Advanced eXtensible InterfaceYou can download AMBA specifications from ARM website also. You have to create an user account and follow the instructions.Cheers !Happy protocol reading ! ...

All terms: AMBA AHB, AMBA APB, AMBA AXI, AMBA Bus, CoreConnect Bus, SoC Design, SoC Integration, System on Chip

System on Chip article links

Posted on 04/14/2009 - 01:15 by from the site ASIC-System On Chip (SoC)-VLSI Design

Recently i came across some System on Chip (SoC) design related articles from design-reuse website. Enjoy good reading:Getting the most from multiprocessor SoC designSoC integration complexities riseChallenges in developing a reusable IP core USB OTG IP case studyA Platform Based SoC Design Environment Verification of IP Core Based SoC'sAnalog IP Integration in SoC: Challenges and Solutions Interface Synthesis in Multiprocessing Systems-On-Chips Techniques for energy-efficient SoC design Using a Versatile, Independent IP Platform for SoC Design Meeting the challenges of 90nm SoC designTop-down SoC Design Methodology Benefits, risks in 90-nm SoC solutionsA Design of System on a Chip for Voice over Wireless LAN SoC IP Interfaces and Infrastructure -- A Hybrid ApproachA PowerPC SOC IO Processor for RAID applications ...

All terms: SoC Design, SoC Integration, System on Chip

Clock Definitions

Posted on 01/19/2009 - 03:53 by from the site ASIC-System On Chip (SoC)-VLSI Design

lock Definitions: Rising and falling edge of the clock For a +ve edge triggered design +ve (or rising) edge is called ‘leading edge’ whereas –ve (or falling) edge is called ‘trailing edge’. For a -ve edge triggered design –ve (or falling) edge is called ‘leading edge’ whereas +ve (or rising) edge is called ‘trailing edge’. Minimum pulse width of the clock can be checked in PrimeTime by using commands given below: set_min_pulse_width -high 2.5 [all_clocks] set_min_pulse_width -low 2.0 [all_clocks] These checks are generally carried out for post layout timing analysis. Once these commands are set, PrimeTime checks for high and low pulse widths and reports any violations. Capture Clock Edge The edge of the clock for which data is detected is known as capture edge. Clock Definitions: Launch Clock Edge This is the edge of the clock wherein data is launched in previous flip flop and will be captured at this flip flop. Skew Skew is the difference in arrival of clock at two consecutive pins of a sequential element is called skew. Clock skew is the variation at arrival time of clock at destination points in the clock network. The difference in the arrival of clock signal at the clock pin of different flops. Two types of skews are defined: Local skew and Global skew. Local skew Local skew is the difference in the arrival of clock signal at the clock pin of related flops. Global skew Global skew is the difference in the arrival of clock signal at the clock pin of non related flops. This also defined as the difference between shortest clock path delay and longest clock path delay reaching two sequential elements. Skew can be positive or negative. When data and clock are routed in same direction then it is Positive skew. When data and clock are routed in opposite direction then it is negative skew. Positive Skew If capture clock comes late than launch clock then it is called +ve skew. Clock and data both travel in same direction. When data and clock are routed in same direction then it is Positive skew. +ve skew can lead to hold violation. +ve skew improves setup time. Negative Skew If capture clock comes early than launch clock it is called –ve skew. Clock and data travel in opposite direction. When data and clock are routed in opposite then it is negative skew. -ve skew can lead to setup violation. -ve skew improves hold time. (Effects of skew on setup and hold will be discussed in detail in forthcoming articles) Uncertainty Clock uncertainty is the time difference between the arrivals of clock signals at registers in one clock domain or between domains. Pre-layout and Post-layout Uncertainty Pre CTS uncertainty is clock skew, clock Jitter and margin. After CTS skew is calculated from the actual propagated value of the clock. We can have some margin of skew + Jitter. Clock Definitions: Clock latency Latency is the delay of the clock source and clock network delay. Clock source delay is the time taken to propagate from ideal waveform origin point to clock definition point. Clock network latency is the delay from clock definition point to register clock pin. Pre CTS Latency and Post CTS Latency Latency is the summation of the Source latency and the Network latency. Pre CTS estimated latency will be considered during the synthesis and after CTS propagated latency is considered. Source Delay or Source Latency It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design". Delay from clock source to beginning of clock tree (i.e. clock definition point). The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design. Network Delay (latency) or Insertion Delay It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register". The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin. Figure below shows example of latency for a design without PLL. Clock Definitions: The latency definitions for designs with PLL are slightly different. Figure below shows latency specifications of such kind of designs. Latency from the PLL output to the clock input of generated clock circuitry becomes source latency. From this point onwards till generated clock divides to flops is now known as network latency. Here we can observe that part of the network latency is clock to q delay of the flip flop (of divide by 2 circuit in the given example) is known value. Clock Definitions: Jitter Jitter is the short-term variations of a signal with respect to its ideal position in time. Jitter is the variation of the clock period from edge to edge. It can vary +/- jitter value. From cycle to cycle the period and duty cycle can change slightly due to the clock generation circuitry. Jitter can also be generated from PLL known as PLL jitter. Possible jitter values should be considered for proper PLL design. Jitter can be modeled by adding uncertainty regions around the rising and falling edges of the clock waveform. Sources of Jitter Common sources of jitter include: Internal circuitry of the phase-locked loop (PLL) Random thermal noise from a crystal Other resonating devices Random mechanical noise from crystal vibration Signal transmitters Traces and cables Connectors Receivers Click here to read more about jitter from Altera. Click here to read what wiki says about jitter. Multiple Clocks If more than one clock is used in a design, then they can be defined to have different waveforms and frequencies. These clocks are known as multiple clocks. The logics triggered by each individual clock are then known as “clock domain”. If clocks have different frequencies there must be a base period over which all waveforms repeat. Base period is the least common multiple (LCM) of all clock periods Asynchronous Clocks In multiple clock domains, if these clocks do not have a common base period then they are called as asynchronous clocks. Clocks generated from two different crystals, PLLs are asynchronous clocks. Different clocks having different frequencies generated from single crystal or PLL are not asynchronous clocks but they are synchronous clocks. Gated clocks Clock signals that are passed through some gate other than buffer and inverters are called gated clocks. These clock signals will be under the control of gated logic. Clock gating is used to turn off clock to some sections of design to save power. Click here to read more about clock gating. Generated clocks Generated clocks are the clocks that are generated from other clocks by a circuit within the design such as divider/multiplier circuit. Static timing analysis tools such as PrimeTime will automatically calculate the latency (delay) from the source clock to the generated clock if the source clock is propagated and you have not set source latency on the generated clock. Clock Definitions: ‘Clock’ is the master clock and new clock is generated from F1/Q output. Master clock is defined with the constraint ‘create_clok’. Unless and until new generated clock is defined as ‘generated clock’ timing analysis tools won’t consider it as generated clock. Hence to accomplish this requirement use “create_generated_clock” command. ‘CLK’ pin of F1 is now treated as clock definition point for the new generated clock. Hence clock path delay till F1/CLK contributes source latency whereas delay from F1/CLK contributes network latency. Virtual Clocks Virtual clock is the clock which is logically not connected to any port of the design and physically doesn’t exist. A virtual clock is used when a block does not contain a port for the clock that an I/O signal is coming from or going to. Virtual clocks are used during optimization; they do not really exist in the circuit. Virtual clocks are clocks that exist in memory but are not part of a design. Virtual clocks are used as a reference for specifying input and output delays relative to a clock. This means there is no actual clock source in the design. Assume the block to be synthesized is “Block_A”. The clock signal, “VCLK”, would be a virtual clock. The input delay and output delay would be specified relative to the virtual clock. read more in: http://www.asic-soc.blogspot.com ...

All terms: Clock definitions, jitter, latency, skew, uncerainty

Transition Delay and Propagation Delay

Posted on 12/15/2008 - 23:47 by from the site ASIC-System On Chip (SoC)-VLSI Design

Transition Delay Transition delay or slew is defined as the time taken by signal to rise from 10 %( 20%) to the 90 %( 80%) of its maximum value. This is known as “rise time”. Transition Delay or Slew Similarly “fall time” can be defined as the time taken by a signal to fall from 90 %( 80%) to the 10 %( 20%) of its maximum value. Transition is the time it takes for the pin to change state. Setting Transition Time Constraints The above theoretical definitions are to be applied on practical designs. Now, the transition time of a net becomes the time required for its driving pin to change logic values (from 10 %( 20%) to the 90 %( 80%) of its maximum value). This transition time used foe delay calculations are based on the timing library (.lib files). Transition related constraints can be provided in Design Compiler (logic synthesis tool from Synopsys) by using below commands: 1. max_transition : This attribute is applied to each output of a cell. During optimization, Design Compiler tries to make the transition time of each net less than the value of the max_transition attribute. 2. set_max_transition: This command is used to change the maximum transition time restriction specified in a technology library. “This command sets a maximum transition time for the nets attached to the identified ports or to all the nets in a design by setting the max_transition attribute on the named objects. For example, to set a maximum transition time of 3.2 on all nets in the design adder, enter the following command: set_max_transition 3.2 [get_designs adder] To undo a set_max_transition command, use the remove_attribute command. For example, enter the following command: remove_attribute [get_designs adder] max_transition” (Directly quoted from Design Complier user manual) Setting Capacitance Constraints The transition time constraints specified above do not provide a direct way to control the actual capacitance of nets. To control capacitance directly, below command has to be used: set_max_capacitance: This command sets the maximum capacitance constraint on input ports or designs. In addition to set_max_transition, set_max_capacitance can also be used as this command works independent. This command applies maximum capacitance limit to output pin or port of the design. This command can also be used to apply capacitance limit on any net. Eg: set_max_capacitance 4 [get_designs decoder] To remove the set_max_capacitance command, use the remove_attribute command. remove_attribute [get_designs decoder] max_capacitance Propagation Delay Propagation delay is the time required for a signal to propagate through a gate or net. Hence if it is cell, you can call it as “Gate or Cell Delay” or if it is net you can call it as “Net Delay” Propagation delay of a gate or cell is the time it takes for a signal at the input pin to affect the output signal at output pin. For any gate propagation delay is measured between 50% of input transition to the corresponding 50% of output transition. There are 4 possibilities: Propagation delay between 50 % of Input rising to 50 % of output rising. Propagation delay between 50 % of Input rising to 50 % of output falling. Propagation delay between 50 % of Input falling to 50 % of output rising. Propagation delay between 50 % of Input falling to 50 % of output falling. Each of these delays has different values. Maximum and minimum values of these set are very important. Maximum and minimum propagation delay values are considered for timing analysis. For net propagation delay is the delay between the time a signal is first applied to the net and the time it reaches other devices connected to that net. Propagation delay is taken as the average of rise time and fall time i.e. Tpd= (Tphl+Tplh)/2. Propagation delay depends on the input transition time (slew rate) and the output load. Hence two dimensional look up tables are used to calculate these delays. How to calculate propagation delay of net and gate? Please refer below articles to find the detailed explanation. How gate delay is calculated? How net delay is calculated? Contamination Delay: Best case delay from valid input to valid output. i.e. minimum propagation delay. read more in: http://www.asic-soc.blogspot.com ...

All terms: Propagation delay, Static Timing Analysis (STA), Timing Analysis, Transition delay

Net Delay or Interconnect Delay or Wire Delay or Extrinsic Delay or Flight Time

Posted on 12/17/2008 - 05:04 by from the site ASIC-System On Chip (SoC)-VLSI Design

titleNet Delay or Interconnect Delay or Wire Delay or Extrinsic Dela/titlespan style="color: rgb(41, 41, 41);"span style="font-size:130%;"bNet Delay or Interconnect Delay or Wire Delay or Extrinsic Delay or Flight Time/b/span/spanspan style="color: rgb(41, 41, 41);" br / br /Net delay is the difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net. br / br //spanspan style="color: rgb(41, 41, 41);"It is due to the finite resistance and capacitance of the net. It is also known as wire delay. br / br //spanspan style="color: rgb(41, 41, 41);"bWire delay =function of (Rnet, Cnet+Cpin) br / br //b/spanspan style="color: rgb(41, 41, 41);"This is output pin of the cell to the input pin of the next cell. br / br //spana onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="http://3.bp.blogspot.com/_Se0VANaI9uM/SPRYqi9e9iI/AAAAAAAAAlI/lFq-PDJaqug/s1600-h/net_delay.jpg"img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="http://3.bp.blogspot.com/_Se0VANaI9uM/SPRYqi9e9iI/AAAAAAAAAlI/lFq-PDJaqug/s400/net_delay.jpg" alt="" id="BLOGGER_PHOTO_ID_5256924153010648610" border="0" //aspan class="fullpost" br / br / span style="font-family:TimesNewRoman,Times New Roman,serif;"Net delay is calculated using Rs and Cs./spanp/p p class="western" align="justify"span style="font-family:TimesNewRoman,Times New Roman,serif;"span style="color: rgb(41, 41, 41);"There are several factors which affect net parasitic:/span/span/p ullip class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"Net Length/span/span/p /lilip class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"Net cross-sectional area/span/span/p /lilip class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"Resistively of material used for metal layers (Aluminum vs. copper)/span/span/p /lilip class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"Number of vias traversed by the net/span/span/p /lilip class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"Proximity to other nets (crosstalk)/span/span/p /li/ulspan style="font-family:TimesNewRoman,Times New Roman,serif;"span style="color: rgb(41, 41, 41);"Post-layout design is annotated with RCs extracted from layout for better accuracy. Annotated RCs override information from WLM./span/span br /p class="western"span style="color: rgb(41, 41, 41);"Interconnect introduces capacitive, resistive and inductive parasites. All three have multiple effects on the circuit behavior./span/p ollip class="western"span style="color: rgb(41, 41, 41);"Interconnect parasites cause an increase in propagation delay (i.e. it slows down working speed)/span/p /lilip class="western"span style="color: rgb(41, 41, 41);"Interconnect parasites increase energy dissipation and affect the power distribution./span/p /lilip class="western"span style="color: rgb(41, 41, 41);"Interconnect parasites introduce extra noise sources, which affect reliability of the circuit. (Signal Integrity effects)/span/p /li/ol p class="western"span style="color: rgb(41, 41, 41);"Dominant parameters determine the circuit behavior at a given circuit node. Non-dominant parameters can be neglected for interconnect analysis./span/p ullispan style="color: rgb(41, 41, 41);"Inductive effect can be ignored if the resistance of the wire is substantial enough-this is the case for long aluminum wires with a small cross section or if the rise and fall times of the applied signals are slow./span/li/ul ullispan style="color: rgb(41, 41, 41);"When the wires are short, the cross section of the wire is large or the interconnect material used has a low resistivity, a capacitive only model can be used./span/li/ul ullispan style="color: rgb(41, 41, 41);"When the separation between neighboring wires is large or when the wires only run together for short distance, inter-wire capacitance can be ignored, and all the parasitic capacitance can be modeled as capacitance to ground./span/li/ul br /p class="western"span style="color: rgb(41, 41, 41);"span style="font-size:130%;"bCapacitance/b/span/span/p p class="western"span style="color: rgb(41, 41, 41);"Capacitance can be modeled by the parallel plate capacitor model./span/p p class="western"span style="color: rgb(41, 41, 41);"C = (ε / t).WL/span/p p class="western"span style="color: rgb(41, 41, 41);"Where /span /p p class="western"span style="color: rgb(41, 41, 41);"ε -- permittivity of dielectric material (SiO2)/span/p p class="western"span style="color: rgb(41, 41, 41);"t -- thickness of dielectric material (SiO2)/span/p p class="western"span style="color: rgb(41, 41, 41);"W -- width of wire /span /p p class="western"span style="color: rgb(41, 41, 41);"L -- length of wire/span/p p class="western"span style="color: rgb(41, 41, 41);"ε -- εsubr/sub εsubo/sub where εsubr/sub -- relative permittivity of SiO2/span/p p class="western"span style="color: rgb(41, 41, 41);"εsubo/sub -- 8.854 x 10-12 F/m; permittivity of free space/span/p p class="western"span style="color: rgb(41, 41, 41);"As technology node shrinks (scaling), to minimize resistance of the wires, it is desirable to keep the cross section of the wire (WxH) as large as possible. But this increases area. Small values of W lead to denser wiring and less area overhead. In advanced process W/H ratio has reduced below unity. Under such circumstances parallel plate capacitance model becomes inaccurate. The capacitance between the sidewall of the wires and substrate called fringing capacitance can no longer be ignored and contributes to the overall capacitance./span/p br /a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="http://1.bp.blogspot.com/_Se0VANaI9uM/SPRYcPRqdvI/AAAAAAAAAlA/QIUbL-yEqdI/s1600-h/cfringe.jpg"img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="http://1.bp.blogspot.com/_Se0VANaI9uM/SPRYcPRqdvI/AAAAAAAAAlA/QIUbL-yEqdI/s400/cfringe.jpg" alt="" id="BLOGGER_PHOTO_ID_5256923907208410866" border="0" //a br / br / meta equiv="CONTENT-TYPE" content="text/html; charset=utf-8"titleNet Delay or Interconnect Delay or Wire Delay or Extrinsic Dela/titlemeta name="GENERATOR" content="OpenOffice.org 1.1.2 (Linux)"meta name="AUTHOR" content="murali"meta name="CREATED" content="20080906;14020000"meta name="CHANGEDBY" content="murali"meta name="CHANGED" content="20081012;2030000" style !-- @page { size: 8.27in 11.69in; margin: 0.79in } P { margin-bottom: 0.08in } -- /style p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"Inter-wire capacitance become dominant factor in multilayer interconnect structures. These floating capacitors (not connected to substrate or ground) form a source of noise (cross talk). This effect is more pronounced for wires in the higher interconnect layer, as these are farther away from the substrate./span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"Generally higher metal layers (i.e. interconnects) have higher thickness (i.e. height) and higher dielectric layers have higher permittivity. Hence these wires display the highest inter-wire capacitance. Hence use it for global signals that are not sensitive to interference. (eg. Supply rails). Or it is advisable to separate wires by an amount that is larger than minimum spacing./span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"span style="font-size:130%;"bResistance/b/span/span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"Resistance R=span style="font-size:130%;" ρ/span.L/ (H.W)=row. L/ Area /span /p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"L -- length/span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"W -- width/span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"span style="font-size:130%;"ρ/span -- resistivity (ohm-m)/span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"Since H (height, thickness) is constant for a given technology we can write: R = rs.(L/W) where Rs=row/H ohm/sqare is called “sheet resistance”./span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"At very high frequencies “skin effect” comes into play such that the resistance becomes frequency dependent. High frequency currents tend to flow primarily on the surface of a conductor, with the current density falling off exponentially with depth into the conductor./span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"Skin effect is only an issue for wider wires. Since clocks tends to carry the highest frequency signals on a chip and also fairly wide to limit resistance, the skin effect likely to have its first impact on these lines. /span /p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"span style="font-size:130%;"bInductance/b/span/span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"With the adoption of low resistance interconnect materials and the increase of switching frequencies to GHz range, inductance starts to an important role. Consequences of on chip inductance include ringing and overshoot effect, reflection of signals due to impedance mismatch, inductive coupling between lines, and switching noise due to (Ldi/dt) voltage drops./span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"span style="font-size:130%;"bLumped Capacitor Model/b/span/span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"As long as the resistive component of the wire is small, and switching frequencies are in the low to medium range, it is meaningful to consider only the capacitive component of the wire, and to lump the distributed capacitance into a single capacitance./span/p br /a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="http://1.bp.blogspot.com/_Se0VANaI9uM/SPRYObsl84I/AAAAAAAAAk4/B7GimmAZLGY/s1600-h/lumped+c+model.jpg"img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="http://1.bp.blogspot.com/_Se0VANaI9uM/SPRYObsl84I/AAAAAAAAAk4/B7GimmAZLGY/s400/lumped+c+model.jpg" alt="" id="BLOGGER_PHOTO_ID_5256923670024418178" border="0" //a br / meta equiv="CONTENT-TYPE" content="text/html; charset=utf-8"titleNet Delay or Interconnect Delay or Wire Delay or Extrinsic Dela/titlemeta name="GENERATOR" content="OpenOffice.org 1.1.2 (Linux)"meta name="AUTHOR" content="murali"meta name="CREATED" content="20080906;14020000"meta name="CHANGEDBY" content="murali"meta name="CHANGED" content="20081012;2030000" style !-- @page { size: 8.27in 11.69in; margin: 0.79in } P { margin-bottom: 0.08in } -- /style p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"The only impact on performance is introduced by the loading effect of the capacitor on the driving gate./span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"span style="font-size:130%;"bLumped RC Model/b/span/span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"If wire length is more than a few millimeters, the lumped capacitance model is inadequate and a resistive capacitive model has to be adopted./span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"In lumped RC model the total resistance of each wire segment is lumped into one single R, combines the global capacitive into single capacitor C./span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"Analysis of network with larger number of R and C becomes complex as network contains many time constants (zeroes and poles). Elmore delay model overcome such problem./span/p p style="margin-bottom: 0in;"span style="color: rgb(41, 41, 41);"span style="font-size:130%;"bElmore Delay Model/b/span/span/p br /a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="http://3.bp.blogspot.com/_Se0VANaI9uM/SPRX_YTjZ3I/AAAAAAAAAkw/Xj47EMHYvqs/s1600-h/elmore+delay+model.jpg"img style="margin: 0px auto 10px; display: block; text-align: center; cursor: pointer;" src="http://3.bp.blogspot.com/_Se0VANaI9uM/SPRX_YTjZ3I/AAAAAAAAAkw/Xj47EMHYvqs/s400/elmore+delay+model.jpg" alt="" id="BLOGGER_PHOTO_ID_5256923411416049522" border="0" //a br /p class="western"span style="color: rgb(41, 41, 41);"Properties of the network:/span/p ullispan style="color: rgb(41, 41, 41);" Has single input node/span/lilispan style="color: rgb(41, 41, 41);" All the capacitors are between a node and ground./span/lilispan style="color: rgb(41, 41, 41);" Network does not contain any resistive loops./span/li/ul p class="western" br //p p class="western"span style="color: rgb(41, 41, 41);"“Path resistance” is the resistance from source node to any other node./span/p p class="western"span style="color: rgb(41, 41, 41);"“Shared path resistance” is the resistance shared among the paths from the source node to any other two nodes./span/p p class="western"span style="color: rgb(41, 41, 41);"Hence,/span/p p class="western"span style="color: rgb(41, 41, 41);"Delay at node 1: Tow d1 = R1C1/span/p p class="western"span style="color: rgb(41, 41, 41);"Delay at node 2: Tow d2= (R1+R2)C2/span/p p class="western"span style="color: rgb(41, 41, 41);"Delay at node 3: Tow d3 = (R1+R2+R3)C3/span/p p class="western"span style="color: rgb(41, 41, 41);"In general:/span/p p class="western"span style="color: rgb(41, 41, 41);"span style="font-size:180%;"τ/spandi=R1C1+(R1+R2)C2+……..+(R1+R2+R3+…..+Ri)Ci/span/p p class="western"span style="color: rgb(41, 41, 41);"If /span /p p class="western"span style="color: rgb(41, 41, 41);"R1=R2=R3=….=R/span/p p class="western"span style="color: rgb(41, 41, 41);"C1=C2=C3=…..C then/span/p p class="western"span style="color: rgb(41, 41, 41);"span style="font-size:180%;"τ/spandi=RC+2RC+……..+nRC/span/p p class="western"span style="color: rgb(41, 41, 41);"Thus Elmore delay is equivalent to the first order time constant of the network./span/p p class="western"span style="color: rgb(41, 41, 41);"Assuming an interconnect wire of length L is partitioned into N identical segments. Each segment has length L/N./span/p p class="western"span style="color: rgb(41, 41, 41);"Then, /span/p p class="western"span style="color: rgb(41, 41, 41);"span style="font-size:180%;"τ/spand=L/N.R.L/N.C+ 2 (L/n.r+L/N.C)+……/span/p p class="western"span style="color: rgb(41, 41, 41);"=(L/N)2(RC+2RC+…….+NRC)/span/p p class="western"span style="color: rgb(41, 41, 41);"=(L/N)2. N(N+1)/span/p p class="western"span style="color: rgb(41, 41, 41);"or span style="font-size:180%;"τ/spand=RC.Lsup2/sup/2/span/p p class="western"span style="color: rgb(41, 41, 41);"= The delay of a wire is a quadratic function of its length/span/p p class="western"span style="color: rgb(41, 41, 41);"= doubling the length of the wire quadruples its delay/span/p p class="western"bspan style="font-size:130%;"span style="color: rgb(41, 41, 41);"Advantages/span/span/b/p ullispan style="color: rgb(41, 41, 41);"It is simple/span/lilispan style="color: rgb(41, 41, 41);"It is always situated between minimum and maximum bounds/span/li/ul p class="western"span style="color: rgb(41, 41, 41);" /span /p p style="font-weight: bold;" class="western"span style="color: rgb(41, 41, 41);font-size:130%;" Disadvantages/span/p ullispan style="color: rgb(41, 41, 41);"It is pessimistic and inaccurate for long interconnect wires./span/li/ulspan style="color: rgb(41, 41, 41);"span style="font-size:130%;"bWire Load Models/b/span/span p class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:Auto,Times New Roman;"Extraction data from already routed designs are used to build a lookup table known as the wire load model (WLM). WLM is based on the statistical estimates of R and C based on “Net Fan-out/span”./span/p br /span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"For fanouts greater than those specified in a wire load table, a “slope factor” is specified for linear extrapolation./span/span p class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"wire_load (“5KGATES”) {/span/span/p p class="western" align="justify"span style="font-family:TimesNewRoman,Times New Roman,serif;"span style="color: rgb(41, 41, 41);"resistance : 0.000271 /spanbspan style="color: rgb(255, 0, 0);"------------- R per unit length/span/b/span/p p class="western" align="justify"span style="font-family:TimesNewRoman,Times New Roman,serif;"span style="color: rgb(41, 41, 41);"capacitance : 0.00017 /spanbspan style="color: rgb(255, 0, 0);"------------- C per unit length/span/b/span/p p class="western" align="justify"span style="font-family:TimesNewRoman,Times New Roman,serif;"span style="color: rgb(41, 41, 41);"slope : 29.4005 /spanbspan style="color: rgb(255, 0, 0);"--------------------- Used for linear extrapolation/span/b/span/p p class="western" align="justify"span style="font-family:TimesNewRoman,Times New Roman,serif;"span style="color: rgb(41, 41, 41);"fanout_length (1, 18.38) /spanbspan style="color: rgb(255, 0, 0);"---------- (fanout = 1, length = 18.38)/span/b/span/p p class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"fanout_length (2, 47.78)/span/span/p p class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"fanout_length (3, 77.18)/span/span/p p class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"fanout_length (4, 106.58)/span/span/p p class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"fanout_length (5, 135.98)/span/span/pp class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"}/span/span/pp class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"b br //b/span/span/pp class="western" align="justify"span style="color: rgb(41, 41, 41);"span style="font-family:TimesNewRoman,Times New Roman,serif;"bEg: /b/span/span /pp class="western" style="margin-left: 0.29in; margin-bottom: 0.2in;" align="justify"span style="color: rgb(41, 41, 41);"span style="color: rgb(41, 41, 41);"bFanout = 7/b/span/span/p br /p class="western" style="margin-left: 0.29in; margin-bottom: 0.2in;" align="justify"span style="color: rgb(41, 41, 41);"span style="color: rgb(41, 41, 41);"Net length = 135.98 + 2 x 29.4005 (slope) = 194.78 /spanspan style="font-family:TimesNewRoman,Times New Roman,serif;"---------- length of net with fanout of 7 br /Resistance = 194.78 x 0.000271 = 0.05279 units br /Capacitance = 194.78 x 0.00017 = 0.03311 units/span/span/pbspan style="font-size:130%;"span style="color: rgb(41, 41, 41);"Wire load models for synthesis/span/span/b p class="western"span style="color: rgb(41, 41, 41);"Wire load modeling allows us to estimate the effect of wire length and fanout on the resistance, capacitance, and area of nets. Synthesizer uses these physical values to calculate wire delays and circuit speeds. Semiconductor vendors develop wire load models, based on statistical information specific to the vendors’ process. The models include coefficients for area, capacitance, and resistance per unit length, and a fanout-to-length table for estimating net lengths (the number of fanouts determines a nominal length)./span/p p class="western"span style="color: rgb(41, 41, 41);"Selection of wire load models in the initial stage (before physical design) depends on the fallowing factors:/span/p p class="western"span style="color: rgb(41, 41, 41);"1. User specification/span/p p class="western"span style="color: rgb(41, 41, 41);"2. Automatic selection based on design area/span/p p class="western"span style="color: rgb(41, 41, 41);"3. Default specification in the technology library/span/p p class="western"span style="color: rgb(41, 41, 41);"Once the final routing step is over in the physical design stage, wire load models are generated based on the actual routing in the design and synthesis is redone using those wire load models./span/p p class="western"span style="color: rgb(41, 41, 41);"In hierarchical designs, we have to determine which wire load model to use for nets that cross hierarchical boundaries. There are three modes for determining which wire load model to use for nets that cross hierarchical boundaries:/span/p p class="western"span style="color: rgb(41, 41, 41);"bTop:/b/span/p p class="western"span style="color: rgb(41, 41, 41);"Applying same wire load models to all nets as if the design has no hierarchy and uses the wire load model specified for the top level of the design hierarchy for all nets in a design and its sub designs. /span /p p class="western"span style="color: rgb(41, 41, 41);"bEnclosed:/b/span/p p class="western"span style="color: rgb(41, 41, 41);"The wire load model of the smallest design that fully encloses the net is applied. If the design enclosing the net has no wire load model, then traverses the design hierarchy upward until we finds a wire load model. Enclosed mode is more accurate than top mode when cells in the same design are placed in a contiguous region during layout. /span /p p class="western"span style="color: rgb(41, 41, 41);"Use enclosed mode if the design has similar logical and physical hierarchies./span/p p class="western"span style="color: rgb(41, 41, 41);"bSegmented:/b/span/p span style="color: rgb(41, 41, 41);"Wire load model for each segment of a net is determined by the design encompassing the segment. Nets crossing hierarchical boundaries are divided into segments. For each net segment, the wire load model of the design containing the segment is used. If the design contains a segment that has no wire load model, then traverse the design hierarchy upward until it finds a wire load model. /spanp class="western" /pspan style="color: rgb(41, 41, 41);"span style="font-size:130%;"bInterconnect Delay vs. Deep Sub Micron Issues/b/span/span p class="western"span style="color: rgb(41, 41, 41);"Performances of deep sub micron ICs are limited by increasing interconnect loading affect. Long global clock networks account for the larger part of the power consumption in chips. Traditional CAD design methodologies are largely affected by the interconnect scaling. Capacitance and resistance of interconnects have increased due to the smaller wire cross sections, smaller wire pitch and longer length. This has resulted in increased RC delay. As technology is advancing scaling of interconnect is also increasing. In such scenario increased RC delay is becoming major bottleneck in improving performance of advanced ICs./span/pp class="western"span style="color: rgb(41, 41, 41);" br //span/ptitleet Delay or Interconnect Delay or Wire Delay or Extrinsic Dela/titlemeta name="GENERATOR" content="OpenOffice.org 1.1.2 (Linux)"meta name="AUTHOR" content="murali"meta name="CREATED" content="20080906;14020000"meta name="CHANGEDBY" content="murali"meta name="CHANGED" content="20081012;2030000" style !-- @page { size: 8.27in 11.69in; margin: 0.79in } P { margin-bottom: 0.08in } --/stylespan style="color: rgb(41, 41, 41);"Here the gate delay and the interconnect delay are shown as functions of various technology nodes ranging from 180nm to 60nm. The interconnect delays shown assumes a line where repeaters are connected optimally and includes the delay due to the repeaters. From the graph it can be observed that with the shrinking of technology gate delay reduces but interconnect delay increases./span p style="margin-bottom: 0in;"span style="font-size:130%;"bLimits of Cu/low-k interconnects/b/span/p p style="margin-bottom: 0in;"At submicron level of 250 nm copper with low-k dielectric was introduced to decrease affects of increasing interconnect delay. But below 130 nm technology node interconnect delays are increasing further despite of introducing low-k dielectric. As the scaling increases new physical and technological effects like biresistivity/i/b and bibarrier thickness/i/b start dominating and interconnect delay increases. Introduction of repeaters to shorten the interconnect length increases total area. The vias connecting repeaters to global layers can cause blockage in lower metal layers. Thus as the technology improves material limitations will dominate factor in the interconnect delay. Increasing metal layer width will cause increase in metallization layer. This can’t be a solution for the problem as it increases complexity, reliability and cost. /p br /p style="margin-bottom: 0in;"Cu low-k dielectric films are deposited by a special process known as biDamascene process/i/b. Adhesion property of Cu with dielectric materials is very poor. Under electric bias they easily drift and cause short between metal layers. To avoid this problem a barrier layer is deposited between dielectric and Cu trench. Even though it decreases effective cross section of interconnects compared to drawn dimensions, it improves reliability. The barrier thickness becomes significant in deep submicron level and effective resistance of the interconnect rises further. In addition to this increasing electron scattering and self heating caused by the electron flow in interconnects due to comparable increase in internal chip temperature also contribute to increase interconnect resistancespan style="font-size:85%;"./span/p/span br /div class="blogger-post-footer"read more in: http://www.asic-soc.blogspot.com/divdiv class="feedflare" a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=dkSBM"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=dkSBM" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=SOF8M"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=SOF8M" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=vfhlM"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=vfhlM" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=0VLGm"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=0VLGm" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=bFh0m"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=bFh0m" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=9OBYM"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=9OBYM" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=8ermM"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=8ermM" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=BuFSm"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=BuFSm" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=YkwsM"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=YkwsM" border="0"/img/a /divimg src="http://feeds.feedburner.com/~r/Asic-systemOnChipsoc-vlsiDesign/~4/420338645" height="1" width="1"/...

All terms: Net delay, Static Timing Analysis (STA)

Delays in ASIC Design

Posted on 09/12/2008 - 02:39 by from the site ASIC-System On Chip (SoC)-VLSI Design

p class="western" style="margin-left: 0.5in; text-indent: -0.5in;" align="justify" We encounter several types of delays in ASIC design. They are as follows:/p ulli Gate delay or Intrinsic delay/lili Net delay or Interconnect delay or Wire delay or Extrinsic delay or Flight time/liliTransition or Slew/liliPropagation delay/liliContamination delay/li/ul p class="western" align="justify"/pspan class="fullpost"p style="text-align: left;" class="western"Wire delays or extrinsic delays are calculated using output drive strength, input capacitance and wire load models. Other delays are intrinsic properties of each and every gate. /p p class="western" align="justify"Delays are interdependent on different electrical properties. [Nekoogar]:/p ulliInput capacitance of the logic gate is a function of output state, output loads and input slew rate./li/ul ulliInternal timing arcs and output slew rate is a function of switching input(s)./li/ul ulliCapacitance of the wire is dependent on frequency./li/ul p class="western" align="justify"br //p ulliInternal timing arcs are a function of input slew rates./li/ul ulliOutput slew rate is a function of input slew rate on each input./li/ul ulliWires exhibit RLC characteristics instead of lumped RC./li/ul p class="western" align="justify" /p p class="western" align="justify"span style="font-size:130%;"bbr //b/span/pp class="western" align="justify"span style="font-size:130%;"bGate Delay/b/span/p p style="text-align: left;" class="western"Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output. [Magma]/p p class="western" style="margin-left: 0.29in; margin-bottom: 0.2in;"/p p class="western" style="margin-left: 0.29in; margin-bottom: 0.2in; font-weight: bold;"Gate delay =function of (input transition (slew) time, Cnet+Cpin)./p p class="western" style="margin-left: 0.29in; margin-bottom: 0.2in;"or /p p class="western" style="margin-left: 0.29in; margin-bottom: 0.2in; font-weight: bold;"Gate delay =function of (input transition (slew) time, Cload)./p p class="western" style="margin-left: 0.29in; margin-bottom: 0.2in;"where Cload=Cnet+Cpin/p p class="western" style="margin-left: 0.29in; margin-bottom: 0.2in;"Cnet--Net capacitance/p p class="western" style="margin-left: 0.29in; margin-bottom: 0.2in;"Cpin--pin capacitance of the driven cell/p p class="western" style="margin-left: 0.29in; margin-bottom: 0.2in;"Cell delay is also same as Gate delay./pbr /br /div style="text-align: center;"a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="http://4.bp.blogspot.com/_Se0VANaI9uM/SLt6koxEfsI/AAAAAAAAAYA/SzwpjCiA_k0/s1600-h/stage_delay.jpg"img style="cursor: pointer;" src="http://4.bp.blogspot.com/_Se0VANaI9uM/SLt6koxEfsI/AAAAAAAAAYA/SzwpjCiA_k0/s400/stage_delay.jpg" alt="" id="BLOGGER_PHOTO_ID_5240917361212817090" border="0" //abr //divbr / p style="margin-bottom: 0in;" align="justify"span style="font-size:130%;"bHow gate delay is calculated?/b/span/p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in; text-align: left;"Cell or gate delay is calculated using bNon-Linear Delay Models (NLDM)/b. NLDM is highly accurate as it is derived from SPICE characterizations. Tbhe delay is a function of the input transition time (i.e. slew) of the cell, the wire capacitance and the pin capacitance of the driven cells./b A slow input transition time will slow the rate at which the cell’s transistors can change state logic 1 to logic 0 (or logic 0 to logic 1), as well as a large output load bCload (Cnet + Cpin)/b, thereby increasing the delay of the logic gate./p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in; text-align: left;"There is another NLDM table in the library to calculate output transition. Output transition of a cell becomes the input transition of the next cell down the chain./p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify"br //p ullip style="margin-bottom: 0in; text-align: left;"Table models are usually two-dimensional to allow lookups based on the binput slew/b and the boutput load (Cload)/b. A sample table is given below./p /li/ul p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify"span style="font-size:85%;"timing() {/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"related_pin : "CKN";/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"timing_type : falling_edge;/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"timing_sense : non_unate;/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"cell_rise(delay_template_7x7) {/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"index_1 ("span style="color: rgb(255, 0, 0);"0.012, 0.032/span, 0.074, 0.154, 0.318, 0.644, span style="background: rgb(255, 255, 0) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"1.3/span");/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"index_2 ("span style="color: rgb(255, 0, 0);"0.001278, 0.0046008/span, 0.0112464, 0.0245376, 0.05112, 0.10454, span style="background: rgb(255, 255, 0) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"0.212148"/span);/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"values ( \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;""span style="color: rgb(255, 0, 0);"0.225894, 0.249015/span, 0.285537, 0.352680, 0.484244, 0.748180, 1.279570", \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"span style="color: rgb(128, 0, 0);""/spanspan style="color: rgb(255, 0, 0);"0.231295, 0.254415/span, 0.290938, 0.358081, 0.489646, 0.753585, 1.284980", \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;""0.243754, 0.266878, 0.303398, 0.370542, 0.502105, 0.766044, 1.297440", \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;""0.267240, 0.290389, 0.326908, 0.394052, 0.525615, 0.789561, 1.320950", \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;""0.307080, 0.330200, 0.366721, 0.433861, 0.565425, 0.829373, 1.360760", \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;""0.380552, 0.403875, 0.440426, 0.507569, 0.639136, 0.903084, 1.434500", \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;""0.497588, 0.521769, 0.558548, 0.625744, 0.757301, 1.021260, span style="background: rgb(255, 255, 0) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"1.552680/span");/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"}/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"rise_transition(delay_template_7x7) {/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"index_1 ("0.012, 0.032, 0.074, 0.154, 0.318, 0.644, 1.3");/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"index_2 ("0.001278, 0.0046008, 0.0112464, 0.0245376, 0.05112, 0.10454, 0.212148");/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"values ( \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;""0.040574, 0.068619, 0.125391, 0.246672, 0.497688, 1.005982, 2.030120", \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;""0.040570, 0.068618, 0.125390, 0.246672, 0.497688, 1.005940, 2.030240", \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;""0.040565, 0.068616, 0.125389, 0.246650, 0.497770, 1.006180, 2.030120", \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;""0.040532, 0.068612, 0.125387, 0.246670, 0.497710, 1.006164, 2.030100", \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;""0.040578, 0.068621, 0.125392, 0.246636, 0.497688, 1.006182, 2.030040", \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;""0.041763, 0.069211, 0.125662, 0.246758, 0.497726, 1.005930, 2.030000", \/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;""0.045813, 0.071321, 0.126671, 0.247154, 0.497846, 1.005962, 2.030180");/span/p p style="margin-bottom: 0in;" align="justify" span style="font-size:85%;"}/span/pbr /p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify"index_1 -- input transition values/p p style="margin-bottom: 0in;" align="justify"index_2-- output load capacitance values/p p style="margin-bottom: 0in;" align="justify"values-- delay values/p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify"span style="font-family:Book Antiqua,serif;"span style="font-size:130%;"bSituation 1: /b/span/span /p p style="margin-bottom: 0in;" align="justify"span style="font-family:Book Antiqua,serif;"bInput transition and output load values match with table index values /b/span /p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in; text-align: left;"If both input transition and output load values match with table index values then corresponding delay value is directly picked up from the delay “values” table as highlighted by yellow shaded data./p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify"span style="font-family:Book Antiqua,serif;"span style="font-size:130%;"bSituation 2: /b/span/span /p p style="margin-bottom: 0in;" align="justify"bOutput load values doesn't match with table index values /b /p p style="margin-bottom: 0in;" align="justify"br //p ullip style="margin-bottom: 0in; text-align: left;"When the actual load capacitance values does not fall directly on or at one of the load-axis index points, the delay is determined by interpolation from the closest points. Note that to carry out interpolation input transition point should match with the any one of the table index values./p /lilip style="margin-bottom: 0in;" align="justify"Determine the equation for the line segment connecting the two nearest points in the table./p /li/ul p style="margin-left: 0.5in; margin-bottom: 0in;" align="justify"br //p p style="margin-left: 0.5in; margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify"To do this first we need to find the slope value./p p style="margin-bottom: 0in; text-align: left;"Slope m = (y2-y1)/(x2-x1) where (y2-y1) is delay segment (generally in ns) on y axis and (x2-x1) is load segment (generally in pf) on x-axis. /p ullip style="margin-bottom: 0in;" align="justify"Solve for the delay at the load point of interest./p /li/ul p style="margin-left: 0.2in; margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify" The linear equation is:/p p style="margin-bottom: 0in;" align="justify"y = mx+c /p p style="margin-bottom: 0in;" align="justify"where /p p style="margin-bottom: 0in;" align="justify"y--delay (ns)/p p style="margin-bottom: 0in;" align="justify"m--slope/p p style="margin-bottom: 0in;" align="justify"x--load capacitance (pf)/p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify"i.e. delay=slope*load point of interest (constant value is zero)/p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify"Load point of interest means load capacitance value for which delay has to be calculated./p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify"span style="font-family:Book Antiqua,serif;"span style="font-size:130%;"bSituation 3: /b/span/span /p p style="margin-bottom: 0in;" align="justify"span style="font-family:Book Antiqua,serif;"bBoth input transition and output load values doesn't match with table index valuesbr //b/span/p p style="margin-bottom: 0in;" align="justify"br //p ullip style="margin-bottom: 0in; text-align: left;"If both input transition and load capacitance values do not match exactly with the look up table index values then bilinear interpolation is used./p /lilip style="margin-bottom: 0in; text-align: left;"Multiple linear interpolations (~3) are performed on multiple closest table data points (~4) as shown in highlighted violet color in the look up table./p /li/ul p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify"span style="font-family:Book Antiqua,serif;"span style="font-size:130%;"bSituation 4: /b/span/span /p p style="margin-bottom: 0in;" align="justify"bOutput load values doesn't match with table index values and is outside the table boundary/b/p p style="margin-bottom: 0in;" align="justify"br //p ullip style="margin-bottom: 0in; text-align: left;"When the load point is outside of the boundary of the index, the delay is extrapolated to the closest known points./p /lilip style="margin-bottom: 0in;" align="justify"Lookup value too far out of range of the given table value could lead to inaccuracy. [Cadence]/p /li/ul p class="western" align="justify"span style="font-size:130%;"bbr //b/span/pp class="western" align="justify"span style="font-size:130%;"bIntrinsic delay/b/span/p p class="western" align="justify"br //p ul style="text-align: left;"liIntrinsic delay is the delay internal to the gate. This is from input pin of the cell to output pin of the cell./li/ul ul style="text-align: left;"liIt is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition. It is caused by the internal capacitance associated with its transistor./li/ul ulliThis delay is largely dependent on the size of the transistors forming the gate because increasing size of transistors increase internal capacitors. /li/ul span style="font-size:130%;"br /span style="font-weight: bold;"References/span/spanbr /br / p style="margin-bottom: 0in;"[Nekoogar] Farzad Nekoogar, “Timing Verification of Application Specific Integrated Circuits”, Prentice Hall/p p style="margin-bottom: 0in;"[Magma] Magma Blast Fusion User Guides/p p style="margin-bottom: 0in;"[Cadence] Cadence SOC Encounter User Guides/p/spandiv class="blogger-post-footer"read more in: http://www.asic-soc.blogspot.com/divdiv class="feedflare" a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=EtBZJL"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=EtBZJL" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=IOq7iL"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=IOq7iL" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=2BycjL"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=2BycjL" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=B1yLrl"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=B1yLrl" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=TEXijl"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=TEXijl" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=OHMXqL"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=OHMXqL" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=vrUl4l"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=vrUl4l" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=DynGDL"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=DynGDL" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=pAXa3l"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=pAXa3l" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=cy3zPL"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=cy3zPL" border="0"/img/a /divimg src="http://feeds.feedburner.com/~r/Asic-systemOnChipsoc-vlsiDesign/~4/380200134" height="1" width="1"/...

All terms: Delays, Gate Delay, Intrinsic Delay, Static Timing Analysis (STA), Timing Analysis

Multi Threshold (MVT) Voltage Technique

Posted on 09/12/2008 - 02:36 by from the site ASIC-System On Chip (SoC)-VLSI Design

p style="margin-bottom: 0in; line-height: 150%;"Multiple threshold voltage techniques use both Low Vt and High Vt cells. Use lower threshold gates on critical path while higher threshold gates off the critical path. This methodology improves performance without an increase in power. Flip side of this technique is that Multi Vt cells increase fabrication complexity. It also lengthens the design time. Improper optimization of the design may utilize more Low Vt cells and hence could end up with increased power!/pspan class="fullpost" p style="margin-bottom: 0in; line-height: 150%;"Ruchir Puri et al. [2] have discussed the design issues related with multiple supply voltages and multiple threshold voltages in the optimization of dynamic and static power. They noted several advantages of Multi Vt optimization. Multi Vt optimization is placement non disturbing transformation. Footprint and area of low Vt and high Vt cells are same as that of nominal Vt cells. This enables time critical paths to be swapped by low Vt cells easily. /p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in; line-height: 150%;"Frank Sill et al. [3] have proposed a new method for assignment of devices with different Vth in a double Vth process. They developed mixed Vth gates. They showed leakage reduction of 25%. They created a library of LVT, mixed Vt, HVT and Multi Vt. They compared simulation results with a LVT version of each design. Leakage power dissipation decreased by average 65% with mixed Vth technique compared to the LVT implementation. /p p style="margin-bottom: 0in;"br //p p style="margin-bottom: 0in; line-height: 150%;"Meeta Srivatsav et al. [4] have explored various ways of reducing leakage power and recommended Multi Vt approach. They have carried out analysis using 130 nm and 90 nm technology. They synthesized design with different combination of target library. The combinations were Low Vt cells only, High Vt cells only, High Vt cells with incremental compile using Low Vt library, nominal (or regular) Vt cell and Multi Vt targeting Hvt and Lvt in one go. With only Low Vt highest leakage power of 469 µw was obtained. With only High Vt cells leakage power consumption was minimum but timing was not met (-1.13 of slack). With nominal Vt moderate leakage power value of 263 µw was obtained. Best results (54 µw with timing met) obtained for synthesis targeting Hvt library and incremental compile using Lvt library./p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in; line-height: 150%;"Different low leakage synthesis flows are carried out by Xiaodong Zhang [1] using Synopsys EDA tools are listed below: /p p style="margin-bottom: 0in;" align="justify"br //p ullibLow-Vt -- Multi-Vt flow/b: This produces least cell count and least dynamic power. But produce highest leakage power. It takes very low runtime. Good for a design with very tight timing constraints/li/ul p style="margin-bottom: 0in;" align="justify"br //p ullibMulti-Vt one pass flow/b: It takesb /blongest runtime and can be used in most of designs./li/ul p style="margin-bottom: 0in;" align="justify"br //p ullibHigh-Vt -- Multi-Vt flow/b: Produce least leakage power consumption but has high cell count and dynamic power. This methodology is good for leakage power critical design./li/ul p style="margin-bottom: 0in;" align="justify"br //p ullibHigh-Vt -- Multi-Vt with different timing constraints flow/b: This is a well balanced flow and produces second least leakage power. This has smaller cell count, area and dynamic power and shorter runtime. This design is also good for most of designs./li/ul p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify"bOptimization Strategies /b /p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in; line-height: 150%;"span style="font-family:Times,serif;"The tradeoffs between the different Vt cells to achieve optimal performance are especially beneficial during synthesis technology gate mapping and placement optimization. The logic synthesis, or gate mapping phase of the optimization process is implemented by synthesis tool, and placement optimization is handled physical implementation tool./span/p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify"bSynthesis /b /p p style="margin-bottom: 0in; line-height: 150%;"span style="font-family:Times,serif;"During logic synthesis, the design is mapped to technology gates. At this point in the process optimal logic architectures are selected, mapped to technology cells, and optimized for specific design goals. Since a range of Vt libraries are now available and choices have to be made across architectures with different Vt cells, logic synthesis is the ideal place to start deploying a mix of different Vt cells into the design. /span /p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in;" align="justify"bSingle-Pass vs. Two-Pass Synthesis –with multiple threshold libraries/b/p p style="margin-bottom: 0in; line-height: 150%;"br //p p style="margin-bottom: 0in; line-height: 150%;"Multiple libraries are currently available with different performance, area and power utilization characteristics, and synthesis optimization can be achieved using either one or more libraries concurrently. In a single-pass flow, multiple libraries can be loaded into synthesis tool prior to synthesis optimization. In a two-pass flow, the design is initially optimized using one library, and then an incremental optimization is carried out using additional libraries. /p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in; line-height: 150%;"About multi vt optimization in his paper Ruchir Puri[2] says: “The multi-threshold optimization algorithm implemented in physical synthesis is capable of optimizing several Vt levels at the same time. Initially, the design is optimized using the higher threshold voltage library only. Then, the Multi-Vt optimization computes the power-performance tradeoff curve up to the maximum allowable leakage power limit for the next lower threshold voltage library. Subsequently, the optimization starts from the most critical slack end of this power-performance curve and switches the most critical gate to next equivalent lower-Vt version. This will increase the leakage in the design beyond the maximum permissible leakage power. To compensate for this, the algorithm picks the least critical gate from the other end of the power-performance curve and substitutes it back with its higher-Vt version. If this does not bring the leakage power below the allowed limit, it traverses further from the curve (from least critical towards more critical) substituting gates with higher-Vt gates, until the leakage limit is satisfied. Then we jump back to the second most critical cell and switch it to the lower-Vt version. This iteration continues until we can no longer switch any gate with the lower vt version without violating the leakage power limit.” /p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in; line-height: 150%;"span style="color: rgb(0, 0, 0);"But Amit Agarwal et al. [5] have warned about the yield loss possibilities due to dual Vt flows. They showed that in nano-scale regime, conventional dual Vt design suffers from yield loss due to process variation and vastly overestimates leakage savings since it doesb /bnot consider junction BTBT (Band To Band Tunneling) leakage into account. Their analysis showedb /bthe importance of considering device based analysis while designing low power schemes like dual Vt. Their research also showed that in scaled technology, statistical information of both leakage and delay helps in minimizing total leakage while ensuring yield with respect to target delay in dual Vt designs. However, nonscalability of the present way of realizing high Vt, requires the use of different process options such as metal gate work function engineering in future technologiesspan style="font-size:85%;"./span/span/p p style="margin-bottom: 0in;" align="justify"br //p p style="margin-bottom: 0in; line-height: 150%;" align="justify"span style="font-size:130%;"bReferences/b/span/p p style="margin-bottom: 0in;"[1] Xiaodong Zhang, “iHigh Performance Low Leakage Design Using Power Compiler and Multi-Vt Libraries/i”, Synopsys, SNUG, Europe, 2003, www.synopsys.com, 10/9/2007/p p style="margin-bottom: 0in;"a name="_Ref190881833"/a[2] Ruchir Puri, “iMinimizing Power Under Performance Constraint/i”, International Conference on Integrated Circuit Design and technology, IEEE, pp.159-163, May 17-20 2004 /p p style="margin-bottom: 0in;"[3] Frank Sill, Frank Grassert and Dirk Timmermann, “iReducing Leakage with Mixed-Vth (MVT)/ib”/b, 18th International Conference on VLSI Design, IEEE, pp.874-877, January 2005/p p style="margin-bottom: 0in;"[4] Meeta Srivatsav, S.S.S.P. Rao and Himanshu Bhatnagar, “iPower Reduction Technique Using Multi-vt Libraries/i”i,/i Fifth International Workshop on System-on-Chip for Real Time Applications, IEEE, pp. 363-367, 2005/p p style="margin-bottom: 0in;"span style="color: rgb(0, 0, 0);"[5] Amit Agannral, Kunhyuk Kang, Swarup K. Bhunia, James D. Gallagher, and Kaushik Roy, “Effectiveness of Low Power Dual-Vt Designs in Nano-Scale Technologies Under Process Parameter Variations”, ACM,i ISLPED’O5, /iAugust 8-10,2005, San Diego, California, USA. 2005. /span /p p style="margin-bottom: 0in;" align="justify"br //p /spandiv class="blogger-post-footer"read more in: http://www.asic-soc.blogspot.com/divdiv class="feedflare" a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=H0qNlyG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=H0qNlyG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=9wSUYSG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=9wSUYSG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=1MsN7OG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=1MsN7OG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=yg2ohEg"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=yg2ohEg" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=CJZSycg"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=CJZSycg" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=q7aSQVG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=q7aSQVG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=Ml3XAig"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=Ml3XAig" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=qSmaVyG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=qSmaVyG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=n3kWIi"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=n3kWIi" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=PMUh6I"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=PMUh6I" border="0"/img/a /divimg src="http://feeds.feedburner.com/~r/Asic-systemOnChipsoc-vlsiDesign/~4/271950020" height="1" width="1"/...

All terms: Low Power Techniques, Multi Vt

Clock Gating

Posted on 12/11/2008 - 19:04 by from the site ASIC-System On Chip (SoC)-VLSI Design

meta name="AUTHOR" content="murali"meta name="CREATED" content="20080301;80000"meta name="CHANGEDBY" content="murali"meta name="CHANGED" content="20080415;20260000" style !-- @page { size: 8.27in 11.69in; margin: 0.79in } H3 { margin-bottom: 0.04in } H3.western { font-family: "Arial", sans-serif; font-size: 13pt } H3.cjk { font-family: "Nimbus Sans L"; font-size: 13pt } H3.ctl { font-family: "Arial", sans-serif; font-size: 13pt } P { margin-bottom: 0.08in } --/stylespan style="color: rgb(0, 0, 0);font-family:times new roman;font-size:100%;" Clock tree consume more than 50 % of dynamic power. The components of this power are: /spanp style="margin-bottom: 0in;font-family:times new roman;" /pspan style="color: rgb(0, 0, 0);font-family:times new roman;font-size:100%;" 1) Power consumed by combinatorial logic whose values are changing on each clock edge/spanspan style="color: rgb(0, 0, 0);font-family:times new roman;font-size:100%;" br /2) Power consumed by flip-flops and/spanspan style="color: rgb(0, 0, 0);font-family:times new roman;font-size:100%;" br /3) The power consumed by the clock buffer tree in the design. /spanp style="margin-bottom: 0in;font-family:times new roman;" /p p style="margin-bottom: 0in;font-family:times new roman;"span style="color: rgb(0, 0, 0);font-size:100%;" It is good design idea to turn off the clock when it is not needed. Automatic clock gating is supported by modern EDA tools. They identify the circuits where clock gating can be inserted./span/p br /span class="fullpost" p style="margin-bottom: 0in;font-family:times new roman;"span style="color: rgb(0, 0, 0);font-size:100%;" RTL clock gating works by identifying groups of flip-flops which share a common enable control signal. Traditional methodologies use this enable term to control the select on a multiplexer connected to the D port of the flip-flop or to control the clock enable pin on a flip-flop with clock enable capabilities. RTL clock gating uses this enable signal to control a clock gating circuit which is connected to the clock ports of all of the flip-flops with the common enable term. Therefore, if a bank of flip-flops which share a common enable term have RTL clock gating implemented, the flip-flops will consume zero dynamic power as long as this enable signal is false./span/p p style="margin-bottom: 0in;font-family:times new roman;" align="justify"span style="color: rgb(0, 0, 0);font-size:100%;" There are two types of clock gating styles available. They are:/span/p p style="margin-bottom: 0in;font-family:times new roman;" align="justify"span style="color: rgb(0, 0, 0);font-size:100%;" 1) Latch-based clock gating br /2) Latch-free clock gating./span/p p style="margin-bottom: 0in;font-family:times new roman;" align="justify"span style="color: rgb(0, 0, 0);font-size:100%;" b br //b/span/pp style="margin-bottom: 0in;font-family:times new roman;" align="justify"span style="color: rgb(0, 0, 0);font-size:130%;" bLatch free clock gating/b/span/p p face="times new roman" style="margin-bottom: 0in;"span style="color: rgb(0, 0, 0);"span style="font-size:100%;"The latch-free clock gating style uses a simple AND or OR gate (depending on the edge on which flip-flops are triggered). Here if enable signal goes inactive in between the clock pulse or if it multiple times then gated clock output either can terminate prematurely or generate multiple clock pulses. This restriction makes the latch-free clock gating style inappropriate for our single-clock flip-flop based design./span /span /p br /div style="text-align: center;"a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="http://bp3.blogger.com/_Se0VANaI9uM/SAbOzKBXwVI/AAAAAAAAATU/XFaTeFp0f84/s1600-h/latch_free_clock_gating.jpeg"img style="cursor: pointer;" src="http://bp3.blogger.com/_Se0VANaI9uM/SAbOzKBXwVI/AAAAAAAAATU/XFaTeFp0f84/s400/latch_free_clock_gating.jpeg" alt="" id="BLOGGER_PHOTO_ID_5190062998849831250" border="0" //a br //divtitle2/title meta name="GENERATOR" content="OpenOffice.org 1.1.2 (Linux)"meta name="AUTHOR" content="murali"meta name="CREATED" content="20080301;80000"meta name="CHANGEDBY" content="murali"meta name="CHANGED" content="20080415;20260000" style !-- @page { size: 8.27in 11.69in; margin: 0.79in } P { margin-bottom: 0.08in } -- /style p style="margin-top: 0.08in; line-height: 150%; text-align: center;" lang="en-GB" span style="color: rgb(0, 0, 0);"span style="font-size:100%;"bLatch free clock gating/b/span/span/p p style="margin-bottom: 0in;" align="justify"bspan style="font-size:130%;"span style="font-family:TimesNewRoman,serif;"span style="color: rgb(0, 0, 0);" br //span/span/span/b/pp style="margin-bottom: 0in;font-family:times new roman;" align="justify"span style="font-size:130%;"bspan style="color: rgb(0, 0, 0);"Latch based clock gating/span/b/span/p p face="times new roman" style="margin-bottom: 0in;"span style="font-size:100%;"span style="color: rgb(0, 0, 0);"The latch-based clock gating style adds a level-sensitive latch to the design to hold the enable signal from the active edge of the clock until the inactive edge of the clock. Since the latch captures the state of the enable signal and holds it until the complete clock pulse has been generated, the enable signal need only be stable around the rising edge of the clock, just as in the traditional ungated design style./span/span/p br /div style="text-align: center;"a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="http://bp0.blogger.com/_Se0VANaI9uM/SAbOZaBXwUI/AAAAAAAAATM/BF529kmvOXk/s1600-h/latch_based_clock_gating.jpeg"img style="cursor: pointer;" src="http://bp0.blogger.com/_Se0VANaI9uM/SAbOZaBXwUI/AAAAAAAAATM/BF529kmvOXk/s400/latch_based_clock_gating.jpeg" alt="" id="BLOGGER_PHOTO_ID_5190062556468199746" border="0" //a br //divp style="margin-top: 0.08in; line-height: 150%; text-align: center;" lang="en-GB"span style="color: rgb(0, 0, 0);"span style="font-size:100%;"b Latch based clock gating/b/span/span/p p style="margin-bottom: 0in; font-family: times new roman;" meta equiv="CONTENT-TYPE" content="text/html; charset=utf-8"title2/titlemeta name="GENERATOR" content="OpenOffice.org 1.1.2 (Linux)"meta name="AUTHOR" content="murali"meta name="CREATED" content="20080301;80000"meta name="CHANGEDBY" content="murali"meta name="CHANGED" content="20080415;20260000" style !-- @page { size: 8.27in 11.69in; margin: 0.79in } P { margin-bottom: 0.08in } -- /style /pp style="margin-bottom: 0in;"span style="color: rgb(0, 0, 0);font-size:100%;" br //span/pp style="margin-bottom: 0in;"span style="color: rgb(0, 0, 0);font-size:100%;" Specific clock gating cells are required in library to be utilized by the synthesis tools. Availability of clock gating cells and automatic insertion by the EDA tools makes it simpler method of low power technique. Advantage of this method is that clock gating does not require modifications to RTL description./span/p p style="margin-bottom: 0in;"span style="font-size:100%;" br //span /p p/p p style="margin-bottom: 0in;" align="justify"span style="font-size:130%;"bReferences/b/span/p p style="margin-bottom: 0in; font-family: times new roman;"span style="color: rgb(0, 0, 0);font-size:100%;" [1] Frank Emnett and Mark Biegel, “Power Reduction Through RTL Clock Gating”, SNUG, San Jose, 2000/span/p p style="margin-bottom: 0in; font-family: times new roman;"span style="color: rgb(0, 0, 0);font-size:100%;" [2] PrimeTime User Guide/span/p /spandiv class="blogger-post-footer"read more in: http://www.asic-soc.blogspot.com/divdiv class="feedflare" a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=ICxM7DG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=ICxM7DG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=Y3yvfDG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=Y3yvfDG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=NlrkYeG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=NlrkYeG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=u7cY2Jg"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=u7cY2Jg" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=5bP7ZTg"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=5bP7ZTg" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=OdIeP6G"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=OdIeP6G" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=ZlsjSEg"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=ZlsjSEg" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=2qVIyMG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=2qVIyMG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=vruSNi"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=vruSNi" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=Vdfu4I"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=Vdfu4I" border="0"/img/a /divimg src="http://feeds.feedburner.com/~r/Asic-systemOnChipsoc-vlsiDesign/~4/271912315" height="1" width="1"/...

All terms: Clock Gating

Multi Vdd (Voltage)

Posted on 12/11/2008 - 19:04 by from the site ASIC-System On Chip (SoC)-VLSI Design

meta equiv="CONTENT-TYPE" content="text/html; charset=utf-8"title2/titlemeta name="GENERATOR" content="OpenOffice.org 1.1.2 (Linux)"meta name="AUTHOR" content="murali"meta name="CREATED" content="20080301;210000"meta name="CHANGEDBY" content="murali"meta name="CHANGED" content="20080415;20490000"style !-- @page { size: 8.27in 11.69in; margin: 0.79in } H3 { margin-top: 0in; margin-bottom: 0in; color: #000000; line-height: 150%; text-align: justify } H3.western { font-family: "Nimbus Roman No9 L", serif; font-size: 12pt; so-language: en-GB } H3.cjk { font-family: "Nimbus Sans L"; font-size: 12pt } H3.ctl { font-family: "Tahoma", "Lucidasans", "Lucida Sans", "Arial Unicode MS"; font-size: 12pt } H5 { margin-top: 0in; margin-bottom: 0in; color: #000000; line-height: 150%; text-align: justify } H5.western { font-family: "Nimbus Roman No9 L", serif; font-size: 12pt; so-language: en-GB } H5.cjk { font-family: "Nimbus Sans L"; font-size: 12pt } H5.ctl { font-family: "Tahoma", "Lucidasans", "Lucida Sans", "Arial Unicode MS"; font-size: 20pt; font-style: italic; font-weight: medium } P { margin-bottom: 0.08in } --/stylemeta equiv="CONTENT-TYPE" content="text/html; charset=utf-8"title2/titlemeta name="GENERATOR" content="OpenOffice.org 1.1.2 (Linux)"meta name="AUTHOR" content="murali"meta name="CREATED" content="20080301;210000"meta name="CHANGEDBY" content="murali"meta name="CHANGED" content="20080415;20490000"style !-- @page { size: 8.27in 11.69in; margin: 0.79in } P { margin-bottom: 0.08in } -- /stylemeta equiv="CONTENT-TYPE" content="text/html; charset=utf-8"title2/titlemeta name="GENERATOR" content="OpenOffice.org 1.1.2 (Linux)"meta name="AUTHOR" content="murali"meta name="CREATED" content="20080301;210000"meta name="CHANGEDBY" content="murali"meta name="CHANGED" content="20080415;20490000"style !-- @page { size: 8.27in 11.69in; margin: 0.79in } P { margin-bottom: 0.08in } --/stylespan style="font-size:100%;"Dynamic power is directly proportional to power supply. Hence naturally reducing power significantly improves the power performance. At the same time gate delay increases due to the decreased threshold voltage. High voltage can be applied to the timing critical path and rest of the chip runs in lower voltage. Overall system performance is maintained. Different blocks having different voltage supplies can be integrated in SoC. This increases power planning complexity in terms of laying down the power rails and power grid structure. Level shifters are necessary to interface between different blocks./span p/p p style="margin-bottom: 0in;" align="justify"/p br /span class="fullpost" br /h5 class="western" align="left" lang="en-GB"Multiple Voltage ASIC/SoC Design: Classification/h5 p style="margin-bottom: 0in;" lang="en-GB" br //p p style="margin-bottom: 0in;" align="justify"Multi voltage design strategies can be broadly classified as follows [1]:/p p style="margin-bottom: 0in;" align="justify" br //p ullibStatic Voltage Scaling (SVS):/b Different but fixed voltage is applied to different blocks or subsystems of the SoC design./li/ul p style="margin-bottom: 0in; line-height: 150%;" br //p ullibMulti-level Voltage Scaling (MVS): /bThe block or subsystem of the ASIC or SoC design is switched between two or more voltage levels. But for different operating modes limited numbers of discrete voltage levels are supported./li/ul p style="margin-bottom: 0in; line-height: 150%;" br //p ullibDynamic Voltage and Frequency Scaling (DVFS): /bVoltage as well as frequency is dynamically varied as per the different working modes of the design so as to achieve power efficiency. When high speed of operation is required voltage is increased to attain higher speed of operation with the penalty of increased power consumption. /li/ul p style="margin-bottom: 0in; line-height: 150%;" br //p ullibAdaptive voltage Scaling (AVS): /bHere voltage is controlled using a control loop. This is an extension of DVFS./li/ul p style="margin-bottom: 0in;" align="justify" br //p p style="margin-bottom: 0in;" align="justify"bMulti Voltage Design Challenges/b/p p style="margin-bottom: 0in;" align="justify" br //p p style="margin-bottom: 0in;" align="justify"bLevel Shifters/b/p p style="margin-bottom: 0in; line-height: 150%;" br //p p style="margin-bottom: 0in; line-height: 150%;"Signals crossing from one voltage domain to another voltage domain have to be interfaced through the level shifter buffers which appropriately shift the signal levels. Design of suitable level shifter is a challenging job./p p style="margin-bottom: 0in;" align="justify" br //p p style="margin-bottom: 0in;" align="justify"bTiming Analysis/b/p p style="margin-bottom: 0in; line-height: 150%;" br //p p style="margin-bottom: 0in; line-height: 150%;" Timing analysis of the given design becomes simpler with the single voltage as it can be performed for single performance point based on the characterized libraries. Tools can optimize the design for worst case PVT (Process, Voltage, temperature) conditions. This is not the case with multi voltage designs. Libraries should be characterized for different voltage levels that are used in the design. EDA tool has to optimize individual blocks or subsystems and also multiple voltage domains. This analysis becomes complex for larger ASIC/SoC./p p style="margin-bottom: 0in;" align="justify" br //p p style="margin-bottom: 0in;" align="justify"bFloor planning and Power Planning/b/p p style="margin-bottom: 0in; line-height: 150%;" br //p p style="margin-bottom: 0in; line-height: 150%;"Multiple power domain demands multiple power grid structure and a suitable power distribution among them. For a larger ASIC/SoC more careful floor planning and power planning is essential. The speed in which different power domains switch on or off is also important. A low voltage power domain may activate early compared to the high voltage domain. Multi voltage designs pose additional board level complexities. Separate power supply may necessary to provide different power levels./p p style="margin-bottom: 0in;" align="justify" br //p p style="margin-bottom: 0in;" align="justify"bMulti Voltage Designs: Timing Issues/b/p p style="margin-bottom: 0in;" align="justify" br //p p style="margin-bottom: 0in;" align="justify"bClock/b/p p style="margin-bottom: 0in; line-height: 150%;" br //p p style="margin-bottom: 0in; line-height: 150%;"Clock Tree Synthesis (CTS) tools should be aware of different power domains and understand the level shifters to insert them in appropriate places. Clock tree is routed through level shifters to reach different power domains. Simultaneous timing analysis and optimization is necessary for multiple voltage domains. Thus CTS becomes more complex in multi voltage designs./p br / br /div style="text-align: center;"a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="http://bp3.blogger.com/_Se0VANaI9uM/SAbUaKBXwWI/AAAAAAAAATc/Ubu7Ga9GIGQ/s1600-h/multi_vdd.jpeg"img style="cursor: pointer;" src="http://bp3.blogger.com/_Se0VANaI9uM/SAbUaKBXwWI/AAAAAAAAATc/Ubu7Ga9GIGQ/s400/multi_vdd.jpeg" alt="" id="BLOGGER_PHOTO_ID_5190069166422868322" border="0" //a br //divtitle2/titlemeta name="GENERATOR" content="OpenOffice.org 1.1.2 (Linux)"meta name="AUTHOR" content="murali"meta name="CREATED" content="20080301;210000"meta name="CHANGEDBY" content="murali"meta name="CHANGED" content="20080415;20490000" style !-- @page { size: 8.27in 11.69in; margin: 0.79in } P { margin-bottom: 0.08in } -- /style p style="margin-top: 0.08in; line-height: 150%; text-align: center;" lang="en-GB" span style="color: rgb(0, 0, 0);"span style="font-size:85%;"bspan style="font-size:100%;"Timing Issues with multi voltage design/span/b/span/span/p p style="margin-bottom: 0in;" align="justify" br //p p style="margin-bottom: 0in;" align="justify"bStatic Timing Analysis (STA)/b/p p style="margin-bottom: 0in; line-height: 150%;" br //p p style="margin-bottom: 0in; line-height: 150%;"Timing analysis for single voltage design is easy. When it comes to static voltage scaling it becomes little tougher job as analysis has to be carried out for different voltages. This methodology requires libraries which are characterized for different voltages used. Multi level and dynamic voltage scaling pose a greater challenge. For each supply voltage level or operating point constraints are specified. There can be different operating modes for different voltages. Constraints need not be same for all modes and voltages. The performance target for each mode can vary. EDA tool should be capable of handling all these situations simultaneously to carry out timing analysis. Different constraints at different modes and voltages have to be satisfied./p p style="margin-bottom: 0in;" align="justify" br //p p style="margin-bottom: 0in;" align="justify"bMulti Voltage Designs: Power Planning Issues/b/p p style="margin-bottom: 0in;" align="justify" br //p p style="margin-bottom: 0in; line-height: 150%;"Efficient power planning is one of the key concerns of modern SoC designs. In multi voltage designs providing power to the different power domains is challenging. Every power domain requires independent local power supply and grid structure and some designs may even have a separate power pad. Separate power pad is possible in flip-chip designs and power pad can be taken out near from the power domain. Other chips have to take out the power pads from the periphery which can put limit to the number of power domains./p p style="margin-bottom: 0in;" align="justify" br //p p style="margin-bottom: 0in; line-height: 150%;"Local on chip voltage regulation is good idea to provide multiple voltages to different circuits. Unfortunately most of the digital CMOS technologies are not suitable for the implementation of either switched mode of operation or linear voltage regulations. Separate power rail structure is required for each power domain. These additional power rails introduce different levels of IR drop putting limit to the achievable power efficiency./p p style="margin-bottom: 0in;" align="justify" br //p p style="margin-bottom: 0in; line-height: 150%;" align="justify"span style="font-size:130%;"bReferences/b/span/p p style="margin-bottom: 0in;"span lang="en-GB"[1] Michael Keating, David Flynn, Robert Aitken, Alan Gibsons and Kaijian Shi, “iLow Power Methodology Manual for System on Chip Design/i”, Springer Publications, NewYork, 2007, www.lpmm-book.org, 4/9/2007/span/p/spandiv class="blogger-post-footer"read more in: http://www.asic-soc.blogspot.com/divdiv class="feedflare" a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=L15P2LG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=L15P2LG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=xcVHGkG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=xcVHGkG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=V6kM1NG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=V6kM1NG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=w67MJCg"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=w67MJCg" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=pcapVug"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=pcapVug" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=rzXXJ8G"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=rzXXJ8G" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=7hLEvdg"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=7hLEvdg" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=RFXRrWG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=RFXRrWG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=jQHuCi"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=jQHuCi" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=9qWkvI"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=9qWkvI" border="0"/img/a /divimg src="http://feeds.feedburner.com/~r/Asic-systemOnChipsoc-vlsiDesign/~4/271920224" height="1" width="1"/...

All terms: Low Power Techniques, Multi Vdd

Multiple Threshold CMOS (MTCMOS) Circuits

Posted on 12/11/2008 - 19:04 by from the site ASIC-System On Chip (SoC)-VLSI Design

title/title meta name="GENERATOR" content="OpenOffice.org 1.1.2 (Linux)"meta name="AUTHOR" content="murali"meta name="CREATED" content="20080301;110000"meta name="CHANGEDBY" content="murali"meta name="CHANGED" content="20080415;20310000" style !-- @page { size: 8.27in 11.69in; margin: 0.79in } H3 { margin-top: 0in; margin-bottom: 0in; color: #000000; line-height: 150%; text-align: justify } H3.western { font-family: "Nimbus Roman No9 L", serif; font-size: 12pt; so-language: en-GB } H3.cjk { font-family: "Nimbus Sans L"; font-size: 12pt } H3.ctl { font-family: "Tahoma", "Lucidasans", "Lucida Sans", "Arial Unicode MS"; font-size: 12pt } P { margin-bottom: 0.08in } --/stylespan lang="en-GB"James T. Kao et al./span [2] showed MTCMOS logic is effective standby leakage control technique, but difficult to implement since sleep transistor sizing is highly dependent on discharge pattern within the circuit block. They showed dual Vt domino logic avoids the sizing difficulties and inherent performance associated with MTCMOS. High Vt cells are used where leakage has to be prevented whereas low Vt cells are employed where speed is of concern. Both cells are effectively used in MTCMOS technique. br /span class="fullpost" br /div style="text-align: center;"a onblur="try {parent.deselectBloggerImageGracefully();} catch(e) {}" href="http://bp2.blogger.com/_Se0VANaI9uM/SAbtD6BXwXI/AAAAAAAAATk/Zzb9xz4kawM/s1600-h/mtcmos.jpeg"img style="cursor: pointer;" src="http://bp2.blogger.com/_Se0VANaI9uM/SAbtD6BXwXI/AAAAAAAAATk/Zzb9xz4kawM/s400/mtcmos.jpeg" alt="" id="BLOGGER_PHOTO_ID_5190096271961473394" border="0" //a br //div br /p style="margin-top: 0.08in; line-height: 150%; text-align: center;" lang="en-GB"span style="color: rgb(0, 0, 0);"span style="font-size:100%;"bMTCMOS technique [1]/b/span/span/p p style="margin-bottom: 0in;"In active mode of operation the high Vt transistors are turned off and the logic gates consisting of low Vt transistors can operate with low switching power dissipation and smaller propagation delay. In standby mode the high Vt transistors are turned off thereby cutting off the internal low Vt circuitry./p p style="margin-bottom: 0in;" align="justify" br //p h3 class="western" align="left" lang="en-GB"Variable Threshold CMOS (VTCMOS)/h3 p style="margin-bottom: 0in;"One of the efficient methods to reduce power consumption is to use low supply voltage and low threshold voltage without loosing speed performance. But increase in the lower threshold voltage devices leads to increased sub threshold leakage and hence more standby power consumption. Variable Threshold CMOS (VTCMOS) devices are one solution to this problem. In VTCMOS technique threshold voltage of the low threshold devices are varied by applying variable substrate bias voltage from a control circuitry./p p style="margin-bottom: 0in;" br /VTCMOS technique is very effective technique to reduce the power consumption with some drawbacks with respect to manufacturing of these devices. VTCMOS requires either twin well or triple well technology to achieve different substrate bias voltage levels at different parts of the IC. The area overhead of the substrate bias control circuitry is negligible. [1]/p p style="margin-bottom: 0in;" br //p p style="margin-bottom: 0in;" align="justify" br //p p style="margin-bottom: 0in;" align="justify"span style="font-size:130%;"bReferences/b/span/p p style="margin-bottom: 0in;"a name="_Ref190881830"/a[1] Sung Mo Kang and Yusuf Leblebici, “iCMOS Digital Integrated Circuits-Analysis and Design/i”, Tata McGraw Hill, Third Edition, New Delhi, 2003/p p style="margin-bottom: 0in;"span lang="en-GB"[2] James T. Kao and Anantha P. Chandrakasani, “Dual-Threshold Voltage Techniques for Low-Power Digital Circuits/i”, IEEE Journal Of Solid-state Circuits, Vol. 35, No. 7, pp.1009-1018, July 2000/span /p p style="margin-bottom: 0in;" lang="en-GB" br //p p style="margin-bottom: 0in;" br //p /spandiv class="blogger-post-footer"read more in: http://www.asic-soc.blogspot.com/divdiv class="feedflare" a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=aTYWWnG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=aTYWWnG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=fv9az0G"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=fv9az0G" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=lfHStoG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=lfHStoG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=S3aA3Pg"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=S3aA3Pg" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=hua6LCg"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=hua6LCg" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=BiMyZNG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=BiMyZNG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=1WkHPsg"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=1WkHPsg" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=WPDmlHG"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=WPDmlHG" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=uRdTii"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=uRdTii" border="0"/img/a a href="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?a=BlaV2I"img src="http://feeds.feedburner.com/~f/Asic-systemOnChipsoc-vlsiDesign?i=BlaV2I" border="0"/img/a /divimg src="http://feeds.feedburner.com/~r/Asic-systemOnChipsoc-vlsiDesign/~4/271965826" height="1" width="1"/...

All terms: Leakage Power, Low Power Techniques, Multi Vt

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