Posted on Monday, January 25, 2010 - 00:37
by JL Gray
from the site Cool Verification
Now that the SystemVerilog 2009 standard has been released, the P1800 working group is getting ready to start work on the next version of the SystemVerilog standard. As part of that effort, they are soliciting feedback in preparation for an...
Posted on Tuesday, October 20, 2009 - 22:13
by JL Gray
from the site Cool Verification
In a fascinating (to me) twist of fate, I will be moderating a panel on the “next big thing” in formal methods at FMCAD 2009 in Austin, Texas. The panel, entitled “What will be the next breakthrough solutions in formal?”...
Posted on Thursday, July 23, 2009 - 10:56
by JL Gray
from the site Cool Verification
Yesterday I presented another full-day workshop on verification planning - this time in Denver. During these workshops I discuss two major topics. First, we discuss a framework to help you understand your design. We break up a design into "efficient"...
Posted on Thursday, November 13, 2008 - 19:48
by JL Gray
from the site Cool Verification
My good friends at Cadence have been gently pinging me for awhile trying to convince me to write about some of their more interesting verification-related announcements. Unfortunately, I’m always in the middle of client work and somehow never get around...
