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Reordering Nets for Low Power
Posted on Sunday, May 10, 2009 - 07:37 by Nir Dahan from the site Adventures in ASIC Digital Design
As posts accumulate, you can see that low power design aspects is a big topic on this site. I try to bring more subtle design examples for lower power design that you can control and implement (i.e. in RTL and the micro architectural stage). Identifying “glitchy” nets is not always easy. Some good candidates are wide parity or CRC calculations (deep and wide XOR trees), complicated arithmetic paths and basically most logic that originates in very wide buses and converges to a single output controlling a specific path (e.g.
Nir Dahan
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Reducing Power Through Retiming
Posted on Monday, February 23, 2009 - 16:46 by Nir Dahan from the site Adventures in ASIC Digital Design
Here is an interesting and almost trivial technique for (potential) power reduction, which I never used myself, nor seen used in others’ designs. Well… maybe I am doing the wrong designs… but I thought it is well worth mentioning. So, if any of my readers use this, please do post a short comment on how exactly did you implement it and if it really resulted in some significant savings. We usually have many high activity nets in the design. They are in many cases toggling during calculation more than once per cycle. Even worse, they often drive long and high capacitive nets.
Nir Dahan
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Arithmetic Tips and Tricks #2 - Another Look at a Slow Adder
Posted on Monday, August 18, 2008 - 16:31 by Nir Dahan from the site Adventures in ASIC Digital Design
Do you remember the old serial adder circuit below? A stream of bits comes in (LSB first) on the FA inputs, the present carry-out bit is registered and fed in the next cycle as a carry in. The sum comes in serially on the output (LSB first). True, it is rather slow - it takes n cycles to add n bits. But hold on, check out the logic depth - one full adder only!!
Nir Dahan
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Low Power Design Techniques
Posted on Tuesday, April 15, 2008 - 02:13 by  from the site ASIC-System On Chip (SoC)-VLSI Design
p style="margin-bottom: 0in;font-family:times new roman;"span style="color: rgb(0, 0, 0);font-size:100%;" span lang="en-GB"Michael Keating et al./span [1] lists several low power techniques to tackle the dynamic and static power consumption in modern SoC designs. Dynamic power control techniques include clock gating, multi voltage, variable frequency, and efficient circuits. Leakage power control techniques include power gating, multi Vt cells.
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