Posted on Thursday, July 15, 2010 - 13:16
by Shankar Hemmady
from the site Verification Martial Arts
As microprocessor designs have grown considerably in complexity, generating microcode stimuli has become increasingly challenging. An article by AMD and Synopsys engineers in EE Times explores using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys VCS constraint solver.
You can find the full article in PDF here.
Posted on Thursday, May 20, 2010 - 21:30
by JL Gray
from the site Cool Verification
As I mentioned earlier in the week, the Universal Verification Methodology – Early Adopter release (UVM-EA) was announced on Monday and can be downloaded from the Accellera website. The process for putting together this release has been both exhilarating and...
Posted on Monday, May 17, 2010 - 10:28
by JL Gray
from the site Cool Verification
Just a quick note - the Universal Verification Methodology Early Adopter (UVM-EA) release is now available on the Accellera website. I'll post additional details on what the release includes later today.
Posted on Wednesday, May 5, 2010 - 17:49
by JL Gray
from the site Cool Verification
I gave a presentation earlier today on the UVM register package survey results. I decided to record a video of the presentation for your viewing pleasure. One thing I didn't address in the video is a question I've received a...
Posted on Sunday, April 11, 2010 - 22:20
by JL Gray
from the site Cool Verification
Some of you may have seen an announcement on Friday describing an early adopter kit of the UVM "based on the Accellera Verification IP Technical Subcommittee (VIP-TSC) decisions to date". Being a member of the Accellera VIP-TSC myself, I can...
Posted on Tuesday, March 9, 2010 - 22:32
by JL Gray
from the site Cool Verification
Many of the Accellera VIP TSC members are in Marlborough, MA this week discussing what features should be part of the first release of the new UVM (Unified Verification Methodology). For those of you who are not familiar, the UVM...
Posted on Tuesday, February 16, 2010 - 23:24
by JL Gray
from the site Cool Verification
In the beginning, there was SystemVerilog, and it was good. Through it some testbenches were made; without it other testbenches were made. In SystemVerilog was light, but also darkness in the form of a set of missing features that had...
Posted on Monday, January 25, 2010 - 00:37
by JL Gray
from the site Cool Verification
Now that the SystemVerilog 2009 standard has been released, the P1800 working group is getting ready to start work on the next version of the SystemVerilog standard. As part of that effort, they are soliciting feedback in preparation for an...
Posted on Tuesday, July 21, 2009 - 10:21
by JL Gray
from the site Cool Verification
I've been having a discussion on Twitter over the last couple of days that the rest of you may find interesting. The question I posed was: "Can someone give me a reason why I would ever use ovm_transaction instead of...
Posted on Sunday, July 19, 2009 - 02:49
by JL Gray
from the site Cool Verification
It's late... very late... and I'm working on slides for one of my DAC presentations, "Zero to Sequences in 30 Minutes". My slides contain source code, and the code is not easy to read. I thought, "Wouldn't it be great...
